From 0c6b4629962de2f80b7ae0eb89ffa5efa7cc957c Mon Sep 17 00:00:00 2001
From: Jerzy Jamroz <jerzy.jamroz@esss.se>
Date: Wed, 22 Jan 2020 11:55:09 +0100
Subject: [PATCH] Supercycle examples - the engine input.

---
 supercycles/example01.csv | 61 +++++++++++++++++++++++++++++++++++++++
 supercycles/example02.csv | 33 +++++++++++++++++++++
 2 files changed, 94 insertions(+)
 create mode 100644 supercycles/example01.csv
 create mode 100644 supercycles/example02.csv

diff --git a/supercycles/example01.csv b/supercycles/example01.csv
new file mode 100644
index 0000000..ae59194
--- /dev/null
+++ b/supercycles/example01.csv
@@ -0,0 +1,61 @@
+Id,Modes,Destination,EVT_BPULSE_ST,EVT_BPULSE_END
+1,Conditioning,ISrc,0,50
+2,Conditioning,LEBT,50,100
+3,Conditioning,MEBT,100,150
+4,ProbeBeam,ISrc,150,200
+5,ProbeBeam,LEBT,200,250
+6,ProbeBeam,MEBT,250,300
+7,FastCommissioning,ISrc,300,350
+8,FastCommissioning,LEBT,350,400
+9,FastCommissioning,MEBT,400,450
+10,RfTest,MEBT,450,500
+11,Conditioning,ISrc,500,550
+12,Conditioning,LEBT,550,600
+13,Conditioning,MEBT,600,650
+14,ProbeBeam,ISrc,650,700
+15,ProbeBeam,LEBT,700,750
+16,ProbeBeam,MEBT,750,800
+17,FastCommissioning,ISrc,800,850
+18,FastCommissioning,LEBT,850,900
+19,FastCommissioning,MEBT,900,950
+20,RfTest,MEBT,950,1000
+21,Conditioning,ISrc,1000,1050
+22,Conditioning,LEBT,1050,1100
+23,Conditioning,MEBT,1100,1150
+24,ProbeBeam,ISrc,1150,1200
+25,ProbeBeam,LEBT,1200,1250
+26,ProbeBeam,MEBT,1250,1300
+27,FastCommissioning,ISrc,1300,1350
+28,FastCommissioning,LEBT,1350,1400
+29,FastCommissioning,MEBT,1400,1450
+30,RfTest,MEBT,1450,1500
+31,Conditioning,ISrc,1500,1550
+32,Conditioning,LEBT,1550,1600
+33,Conditioning,MEBT,1600,1650
+34,ProbeBeam,ISrc,1650,1700
+35,ProbeBeam,LEBT,1700,1750
+36,ProbeBeam,MEBT,1750,1800
+37,FastCommissioning,ISrc,1800,1850
+38,FastCommissioning,LEBT,1850,1900
+39,FastCommissioning,MEBT,1900,1950
+40,RfTest,MEBT,1950,2000
+41,Conditioning,ISrc,2000,2050
+42,Conditioning,LEBT,2050,2100
+43,Conditioning,MEBT,2100,2150
+44,ProbeBeam,ISrc,2150,2200
+45,ProbeBeam,LEBT,2200,2250
+46,ProbeBeam,MEBT,2250,2300
+47,FastCommissioning,ISrc,2300,2350
+48,FastCommissioning,LEBT,2350,2400
+49,FastCommissioning,MEBT,2400,2450
+50,RfTest,MEBT,2450,2500
+51,Conditioning,ISrc,2500,2550
+52,Conditioning,LEBT,2550,2600
+53,Conditioning,MEBT,2600,2650
+54,ProbeBeam,ISrc,2650,2700
+55,ProbeBeam,LEBT,2700,2750
+56,ProbeBeam,MEBT,2750,2800
+57,FastCommissioning,ISrc,2800,2850
+58,FastCommissioning,LEBT,2850,2900
+59,FastCommissioning,MEBT,2900,2950
+60,RfTest,MEBT,2950,3000
diff --git a/supercycles/example02.csv b/supercycles/example02.csv
new file mode 100644
index 0000000..3a8b020
--- /dev/null
+++ b/supercycles/example02.csv
@@ -0,0 +1,33 @@
+Id,Modes,Destination,EVT_BPULSE_ST,EVT_BPULSE_END
+1,Conditioning,ISrc,0,5
+2,Conditioning,LEBT,0,50
+3,Conditioning,MEBT,0,100
+4,ProbeBeam,ISrc,0,200
+5,ProbeBeam,LEBT,0,300
+6,ProbeBeam,MEBT,0,400
+7,FastCommissioning,ISrc,0,500
+8,FastCommissioning,LEBT,0,600
+9,FastCommissioning,MEBT,0,700
+10,RfTest,MEBT,0,800
+11,Conditioning,ISrc,0,900
+12,Conditioning,LEBT,0,1000
+13,Conditioning,MEBT,0,1100
+14,ProbeBeam,ISrc,0,1200
+15,ProbeBeam,LEBT,0,1300
+16,ProbeBeam,MEBT,0,1400
+17,FastCommissioning,ISrc,0,1500
+18,FastCommissioning,LEBT,0,1600
+19,FastCommissioning,MEBT,0,1700
+20,RfTest,MEBT,0,1800
+21,Conditioning,ISrc,0,1900
+22,Conditioning,LEBT,0,2000
+23,Conditioning,MEBT,0,2100
+24,ProbeBeam,ISrc,0,2200
+25,ProbeBeam,LEBT,0,2300
+26,ProbeBeam,MEBT,0,2400
+27,FastCommissioning,ISrc,0,2500
+28,FastCommissioning,LEBT,0,2600
+29,FastCommissioning,MEBT,0,2700
+30,RfTest,MEBT,0,2800
+31,Conditioning,ISrc,0,2900
+32,Conditioning,LEBT,0,3000
-- 
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