Use fixed PCI BAR size
Map 16 MB of memory for register access. This enables efficient register access with the unmodified xdma driver from Xilinx.
16 MB is the BAR size used in the ESS FPGA Framework.
Edited by Andreas Persson
Map 16 MB of memory for register access. This enables efficient register access with the unmodified xdma driver from Xilinx.
16 MB is the BAR size used in the ESS FPGA Framework.